PURPOSE: To attain a stable operation at a high speed by using an output of a frequency divider circuit inputting an output of a prescaler and a carry of 1st and 2nd programmable counters for a frequency division ratio control signal of the prescaler.
CONSTITUTION: A prescaler 1 frequency-divides a signal inputted from an input terminal 11 according to a carry output of a 3-bit counter 4. The frequency division ratio is 1/6 when a level of a control input terminal 13 is at an L level and 1/5 when the level of a control input terminal 13 is at an H level. An output of a 6-bit counter 2 is given to initial value load control signal input terminals 22, 42 of the counter 2 and the 3-bit counter 4. The initial value of the counters 2, 3 is given from 1st and 2nd initial value input terminals 25, 45. A frequency division ratio control circuit 5 keeps its output to H till a carry of the counter 2 is produced after the carry of the counter 4 is first generated and gives its output to a terminal 13.
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ADACHI HISASHI
MARUYAMA MASAKATSU
