PURPOSE: To extract plural frequency division signals whose frequency division ratio differs from each other from one fixed frequency divider at a high speed switching.
CONSTITUTION: A 1/8 frequency divider 3 receiving an input signal S1 produces a 1/2 frequency division signal S2, a 1/4 frequency division signal S3 and a 1/8 frequency division signal S4 respectively from 1/2 frequency dividers 32,33,34 connected in cascade. Analog switches 4,5,6 apply on/off control to the frequency division signals S2,S3 and S4 respectively in response to control signals C1,C3,C4. A decoder 1 produces the control signals C1,C3,C4 in response to digital signals CA,CB fed externally. The analog switches 4,5,6 provide an output of any of the frequency division signals S2,S3,S4 whose frequency division ratio differs according to the digital signals CA,CB to a signal output terminal 104.
JPS5943780 | [Title of the Invention] Data transfer signal generation circuit |
JPS63290409 | FREQUENCY DIVISION CIRCUIT |
JPWO2010004747 | Multiphase clock divider circuit |
JPS61287321A | 1986-12-17 |