PURPOSE: To check a product easily and quickly by constituting the frequency divider so that the initial setting can be performed by giving a reset signal externally.
CONSTITUTION: When a reset signal 9 is logical 1 and a count value of a counter 1 becomes a prescribed value (e.g., M), a load signal 5 is logical 0, a frequency division designating signal 3 (e.g., N) is read, a count-up operation is performed by a clock signal 2, and when the count value reaches the M, the frequency dividing operation is performed by repeating the said operation again. When the reset signal 9 is logical 0, an output of an AND circuit 13 goes to 0 independently of the output value of the signal detecting circuit 10, and a programmable counter 1 reads the frequency dividing signal 3 (e.g., N). Further, when the reset signal 9 goes to a high level, the count-up operation by the clock signal 2 is started while starting from the count value N.
| JPS6382020 | COUNTING CIRCUIT WITH COMPARING FUNCTION |
| JPH02184113 | FREQUENCY DIVIDER |
MUROTA KAZUAKI
KIMURA TADAKATSU
MATSUURA TAKASHI
URIYA SUSUMU
NIPPON ELECTRIC CO
| JPS50145069A | 1975-11-21 |