PURPOSE: To provide a low power consumption variable frequency dividing circuit.

CONSTITUTION: When a control signal MCa is 'L', output from an AND gate 131 goes 'L' regardless of the level of feedback signal from a D-FF110-1 and an OR gate 141 transmits a feedback signal from the negative phase output terminal Q/ of a D-FF12O, as it is, to an input terminal D ot the D-FF110-1. In this regard, the D-FF110-1 and 120-1 perform frequency dividing operation by four. When the control signal CMa is 'H', the AND gate 131 delivers a feedback signal from the negative phase output terminal Q/ of the D-FF110-1, as it is, to the input terminal of the OR gate 141. Consequently, the D-FF110-1, 120-1 and OR gate 141 perform frequency dividing operation by three.