PURPOSE: To easily the shift to the high frequency side of a frequency range by inputting the output of a variable frequency division operating means to the input of a 2nd logic circuit being a fixed frequency dividing circuit and using the output therefrom as an input to the control terminal of the variable frequency division operating means so as to decrease the delay difference between two input signals of the frequency division operating means.

CONSTITUTION: A variable frequency dividing circuit 13 consists of a DFF1 circuit 3, a DFF2 circuit 4, a DFF3 circuit 5, a NOR1 circuit 6, a NOR2 circuit 17, N TFF circuits 91-9n and an OR circuit 18. By such constitution, odd number and even number of frequency dividing switching control elements 10 are used and when they are at a high level, an input to the input terminal D2 of the circuit 6 is always brought into a low level, a data inputted to the terminal D1 is inverted and outputted from an output terminal Q. Thus, the circuit 3, 4 are connected in cascade and the output from the output terminal Q of the circuit 4 is fed back to the input terminal D1 of the circuit 6 and the output from an output terminal QB is outputted to the circuit 17 and the output from the output terminal Q of the circuit 5 is fed back to the circuit 6. Thus, the output signal is subjected to 1/2n frequency division by the circuits 91-9n.