Title:
VARIABLE FREQUENCY DIVISION DEVICE
Document Type and Number:
Japanese Patent JP2012222793
Kind Code:
A
Abstract:
To provide a variable frequency division device that is compliant with a fast clock signal.
A variable frequency division circuit 101 inputs a clock signal Clk_a, and outputs a signal Do1 that is a frequency division of the clock signal Clk_a by a factor of P (P is an integer of two or greater) or P+1. A variable frequency division circuit 102 inputs a clock signal Clk_b having the opposite phase to the clock signal Clk_a, and outputs a signal Do2 that is a frequency division of the clock signal Clk_b by a factor of P or P+1. A path switching circuit 103 inputs the signals Do1, Do2 and selectively outputs either of the signals Do1, Do2 according to a path selection signal MuxCont.
Inventors:
ANDO NOBUHIKO
NAKAMIZO HIDEYUKI
NAKAMIZO HIDEYUKI
Application Number:
JP2011090197A
Publication Date:
November 12, 2012
Filing Date:
April 14, 2011
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K21/00; H03K23/64; H03L7/197
Attorney, Agent or Firm:
Hideaki Tazawa
Hamada Hatsune
Hamada Hatsune
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