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Title:
VARIABLE GAIN AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JPH09260978
Kind Code:
A
Abstract:

To provide the variable gain amplifier circuit reducing an offset of an output obtained by amplifying two input difference signals.

An output of a variable gain circuit 1 that receives 1st and 2nd input signals at input terminals 2, 3 and controls a synthesis ratio of the 1st and 2nd input signals with a control signal and an output of a differential amplifier 5 amplifying a difference between the 1st and 2nd input signals are summed by an adder 4, which provides an output. Since the output from the variable gain circuit 1 is decreased by the addition of the output from the differential amplifier 5 with respect to a desired output signal, even when a wide dynamic range is required for the variable gain circuit 1, an output dynamic range of the variable gain circuit 1 is decreased and then an output offset of the variable gain circuit 1 caused by component mis-matching is reduced.


Inventors:
KAKITSUKA YASUHIRO
FUJII TOSHIKAZU
Application Number:
JP6332196A
Publication Date:
October 03, 1997
Filing Date:
March 19, 1996
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11B11/00; H03F3/45; H03F3/68; (IPC1-7): H03F3/68; G11B11/00; H03F3/45
Attorney, Agent or Firm:
Suyama Saichi



 
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