PURPOSE: To realize a technique which eliminates the skew error between a non-divided signal and a 2-divided signal of a variable 2 frequency dividing circuit.
CONSTITUTION: A variable 2 frequency dividing circuit 100 provided with a D type latch circuit 101 which takes the noninverted output of a D type latch circuit 103 as the input and performs the latch operation in accordance with a clock signal Φi, a selection circuit 102 which takes the inverted output of the D type latch circuit 101 as the input and performs the latch operation in accordance with a clock signal Φ and selects an outputted frequency divided signal by an output select signal SEL, and the D type latch circuit 103 which outputs the inverted output as the frequency divided signal eliminates the skew error between selectively outputted non-divided signal and 2 divided signal.
JPS5943844 | [Title of the Invention] Oscillator |
JPS60197011 | CR OSCILLATING CIRCUIT |
TATEZAWA TAKESHI
HITACHI MICROCOMPUTER SYST