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Title:
VARIABLE HALVED FREQUENCY DIVIDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH08335859
Kind Code:
A
Abstract:

PURPOSE: To realize a technique which eliminates the skew error between a non-divided signal and a 2-divided signal of a variable 2 frequency dividing circuit.

CONSTITUTION: A variable 2 frequency dividing circuit 100 provided with a D type latch circuit 101 which takes the noninverted output of a D type latch circuit 103 as the input and performs the latch operation in accordance with a clock signal Φi, a selection circuit 102 which takes the inverted output of the D type latch circuit 101 as the input and performs the latch operation in accordance with a clock signal Φ and selects an outputted frequency divided signal by an output select signal SEL, and the D type latch circuit 103 which outputs the inverted output as the frequency divided signal eliminates the skew error between selectively outputted non-divided signal and 2 divided signal.


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Inventors:
OISHI TOSHIHISA
TATEZAWA TAKESHI
Application Number:
JP16473895A
Publication Date:
December 17, 1996
Filing Date:
June 07, 1995
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICROCOMPUTER SYST
International Classes:
H03K3/02; H03K3/037; H03K23/64; H03L7/08; (IPC1-7): H03K3/02; H03K3/037; H03K23/64; H03L7/08
Attorney, Agent or Firm:
Tamamura Shizuyo