Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
VARIABLE LENGTH CODE WORD DECODING SYSTEM
Document Type and Number:
Japanese Patent JPH03198576
Kind Code:
A
Abstract:

PURPOSE: To simplify the decoding processing and to attain high speed processing by adding a fixed data with a fixed length to a head of a coding data inputted to a decoding table so as to distinguish a high-order invalid data and a low-order valid data of the decoding object data.

CONSTITUTION: Since a fixed data '1' is set to the least significant bit as a decoding object data, a detection flag 4 is naturally '0' and an event 5 has no meaning. Then in the processing step 2, a succeeding bit data '0' of a coding data 2 is inputted and a low-order bit is recognized as a valid data from the fixed data (first '1' from the most significant digit) in a decoding table 1 and the detection flag 4 is outputted. Then in the processing step 3, similarly to the processing step 2, a succeeding bit data '0' of the coding data 2 is inputted. Then in the processing step 4, a succeeding bit data '1' of the coding data 2 is inputted and a valid data '001' is recognized similarly. The detection flag 4 is '1' and when a CPU detects it, an event 5 is read and the decoding of an event (c) is recognized.


Inventors:
HORII KAZUYA
Application Number:
JP33936489A
Publication Date:
August 29, 1991
Filing Date:
December 27, 1989
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04N1/419; (IPC1-7): H04N1/419
Attorney, Agent or Firm:
Hiroaki Tazawa (1 person outside)



 
Previous Patent: コンクリート型枠

Next Patent: VACUUM CLEANER