Title:
VARIABLE LOGICAL INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3486725
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To lessen the occupation area of a wiring region smaller than that of a variable logical block so as to make the chip size small, by arranging a variable logic block and a switch matrix in checker flag form, and providing a wiring region for interblock connection above the variable logic block.
SOLUTION: This circuit is equipped with one piece of semiconductor substrate SUB such as single crystal silicon, a variable logic block PLB whose logical function can be changed from outside, and a switch matrix SMX as a variable wiring circuit whose interwiring connection state can be changed from outside. The variable logical block PLB and the switch matrix SMX are arranged so as to constitute a checker flag pattern as a whole. Furthermore, a wiring region for connection between blocks is provided above the variable logical block PLB by applying a multilayer wiring art. Hereby, the rate of occupation area of the switch matrix SMX to that of the variable block PLB is reduced, whereby the chip size can be downed.
Inventors:
Mitsugu Kusunoki
Nobuo Tanba
Nobuo Tanba
Application Number:
JP30873395A
Publication Date:
January 13, 2004
Filing Date:
November 28, 1995
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/82; H03K19/177; (IPC1-7): H01L21/82
Domestic Patent References:
| JP4130749A |
Attorney, Agent or Firm:
Tomio Ohinata