PURPOSE: To easily integrate a variable pulse width circuit and to easily obtain a pulse width adjusted value with the circuit by constituting signal transmission lines in such a way that the OR or AND of signals propagated from arbitrary two of the signal transmission lines can be outputted.

CONSTITUTION: Each paired transfer gates T11 and T12 to Tn1 and Tn2 simultaneously operate and two of plural signal transmission lines L1-Ln are activated. When for example, control voltages VR1 and VR2 are applied across the gate pairs T11 and T12 and T21 and T22 and other lines L3-Ln are blocked, input signals are propagated to the lines L1 and L2 through buffers B0, B1, and B2. The lines L1 and L2 delay the propagated signals in accordance with the capacitance values of capacities C1 and C2. Accordingly, an AND gate A0 to which signals P1 and P2 are inputted sets output signals at 'H' only during the period in which the signals P1 and P2 are 'H'. Therefore, a desired pulse width can be easily obtained, since the pulse width of the output signal of the gate A0 changes in corresponding to the difference in delayed amount between the lines L1 and L2, and this variable pulse width circuit can easily be integrated.