PURPOSE: To vary the processing speed in terms of hardware, i.e., by means of a circuit technology by using a vertical synchronizing signal of a video signal and the reading and writing signal of a video display processor to intermittently set a central processing unit under pause states.

CONSTITUTION: A monostable multivibrator 15 contains resistors 15a and 15b which decide the time constants and can vary its pause period. The vertical clock signal VCLK received from an input terminal 10 varies as shown in a figure B and a time difference is produced between signals S1 and S2 obtained from an output terminal Q of a monostable multivibrator 15 and an inverted output terminal Q of a monostable multivibrator 16 respectively as shown in figures C and D. Then the reading and writing signals are applied to a VDP 5. When the writing signal, the inverse of VDPW or the reading signal, the inverse of VDPR to be applied to an input terminal 13 or 14 is set at a low level as shown in a figure F. Thus the output signal S6 of an AND circuit 21 is also set at a low level as shown in a figure H. The low level of the signal S3 supplied to an input terminal D of an FF circuit 18 is fetched at the rise edge of the signal S6. Then a request for pause is given to a CPU 1.