Title:
Vector processing engine with marsing circuit between execution unit and vector data memory and related methods
Document Type and Number:
Japanese Patent JP6339197
Kind Code:
B2
Abstract:
Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.
Inventors:
Khan, Laher
Application Number:
JP2016531030A
Publication Date:
June 06, 2018
Filing Date:
November 14, 2014
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F17/16; G06F9/30; G06F9/38
Domestic Patent References:
| JP2008535115A | ||||
| JP2008165279A |
Foreign References:
| WO2010087144A1 |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
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