Title:
VECTOR PROCESSOR
Document Type and Number:
Japanese Patent JPS60136870
Kind Code:
A
Abstract:
PURPOSE:To reduce the total number of chains, to actuate a resource efficiently and to reduce vector processing time by executing two reading operations in parallel with one vector register. CONSTITUTION:Vector instructions to be executed are successively applied to a vector register control unit 1, a vector register starting circuit 2 executes necessary decoding and the decoded vector instructions are applied to a vector register control circuit 3 and a vector register data unit 4 through starting signal lines 21, 22 respectively. Writing operation is executed in accordance with a signal outputted from a writing signal line 31 and data 5 sent from the resource are written in a VR-RAM6. The 1st reading operation is executed in accordance with a signal outputted from the 1st reading signal line 32 to read out the contents of the VR-RAM6 and send the read-out data as operand data 7. Similarly, the 2nd reading operation is executed on the basis of the 2nd reading signal line 33.
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Inventors:
ABE HITOSHI
Application Number:
JP24388483A
Publication Date:
July 20, 1985
Filing Date:
December 26, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F9/38; G06F12/00; G06F15/78; G06F17/16; (IPC1-7): G06F9/38; G06F13/16; G06F15/347
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)