Title:
VECTOR PROCESSOR
Document Type and Number:
Japanese Patent JPS63174174
Kind Code:
A
Abstract:
PURPOSE:To remove a defect in an exception informing processing and to inform required information by providing an F control circuit for informing the fastest exception, a Q control circuit for interrupting the start of a vector instruction and a storing circuit for holding the exception information. CONSTITUTION:Various types of logic circuits in a vector processor 4 and a scalar processor 3 form the F control circuit, the Q control circuit and the storing circuit. When the exception is generated in the device, the faster exception information in time is informed to a supervisor by the F control circuit. Simultaneously, the vector instruction start is interrupted by the Q control circuit. The supervisor reads the storage to inform what is happened in to a user. The user sets information meaning a serial execution instruction to a vector processing control bit in a vector processing execution control storing area in order to know the exception corresponding to the sentence of a program language. Thereby, the exception information having the meaning to the user, namely, the exception information corresponding to the sentence can be obtained.
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Inventors:
AOYAMA TOMOO
MURAYAMA HIROSHI
MURAYAMA HIROSHI
Application Number:
JP579687A
Publication Date:
July 18, 1988
Filing Date:
January 13, 1987
Export Citation:
Assignee:
HITACHI LTD
HITACHI COMPUTER ENG
HITACHI COMPUTER ENG
International Classes:
G06F17/16; G06F15/78; (IPC1-7): G06F15/347
Attorney, Agent or Firm:
Masatoshi Isomura