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Patent Searching and Data


Title:
VERTICAL THINNING CIRCUIT
Document Type and Number:
Japanese Patent JPH0418874
Kind Code:
A
Abstract:

PURPOSE: To generate a thinned signal so that the information of an original video signal is included without an omission by apportionment in accordance with reduction ratio by changing the selection mode of a multiplexer according to the rate of the omission of the thinned signal for reducing the input video signal.

CONSTITUTION: A luminance signal is introduced to an input terminal 21, and is inputted to a delaying means in which one-line delay circuits 22,23 are connected in series, and simultaneously, it is supplied to coefficient multipliers 31,32. The output of the one-line delay circuit 22 is supplied to the coefficient multipliers 33,34, and the output of the one-line delay circuit 23 is inputted to the one-line delay circuits 35,36, and the outputs of the coefficient multipliers 31 to 36 are supplied to the multiplexers 37 to 39, and are supplied to an adder 40. Here, the multiplexers 37 to 39 are changed into the mode to select the outputs of the coefficient multipliers 31, 33, 35 and the mode to select the outputs of the coefficient multipliers 32, 34, 36. Thus, in the case of obtaining a reduced picture, the thinned signal can be generated so that the information of the original video signal is included without an omission by the apportionment in accordance with the reduction ratio.


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Inventors:
ICHIHARA KIYOSHI
Application Number:
JP11990890A
Publication Date:
January 23, 1992
Filing Date:
May 11, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA AVE KK
International Classes:
H04N5/262; H04N1/393; H04N7/01; (IPC1-7): H04N5/262
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)