Title:
VERTICAL WAFER BOAT
Document Type and Number:
Japanese Patent JP3125968
Kind Code:
B2
Abstract:
PURPOSE: To minimize a maximum shearing stress applied to a wafer and avoid the slippage dislocation by a method wherein respective stored semiconductors are supported at 3 points, i.e., the wafer insertion groove of a wafer pillar and the wafer insertion grooves formed on two wafer support members.
CONSTITUTION: Four wafer support members 2 of which a vertical wafer boat 1 is composed are arranged on the one side half of a wafer circumference at approximately regular intervals. The top and bottom end parts of the respective wafer support members 2 are fixed to an upper support plate 3 and a lower support plate 4. When the step parts 8 and 8 of a wafer pillar 5 are detachably attached to the cut trenches 6 and 7 of the upper support plate 3 and the lower support plate 4, U-shaped spacers 9 having thicknesses (h) are attached to the step parts 8 and 8 from the upper surface of the upper support plate 3 and from the inside of the lower support plate 4.
Inventors:
Atsushi Yoshikawa
Hideo Nakanishi
Katsuhiro Chaki
Junichi Matsushita
Takeo Hayashi
Yoshio Kirino
Hideo Nakanishi
Katsuhiro Chaki
Junichi Matsushita
Takeo Hayashi
Yoshio Kirino
Application Number:
JP26209294A
Publication Date:
January 22, 2001
Filing Date:
September 30, 1994
Export Citation:
Assignee:
Toshiba Ceramics Co., Ltd.
International Classes:
H01L21/22; H01L21/31; (IPC1-7): H01L21/22; H01L21/31
Domestic Patent References:
| JP4148550A | ||||
| JP566990U |
Attorney, Agent or Firm:
Shigeru Kinoshita