PURPOSE: To reduce the number of the wirings of the bus lines between the title video memory controller and a video memory to store the video data of plural planes by accessing the video memory in a static column mode and parallel-serial converting the video data.

CONSTITUTION: A timing control circuit 23 sends a low address to a video memory 10 and successively sends column addresses corresponding to respective planes. The video data of the respective planes are successively read out on a data bus 30 according to the address sending processing. Further, the timing control circuit 23 instructs respective shift registers 21 to latch the video data of corresponding planes to be read out in synchronism with the column address sending processing and converts the latched video data into the one having a serial format by reading out the latched video data at a point where the latching of the video data for all the planes is completed. Thus, the number of the wirings between the video memory controller and the video memory 10 can be reduced.