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Title:
VIDEO SIGNAL DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH0314367
Kind Code:
A
Abstract:

PURPOSE: To automatically set up a delay time difference between respective signals to an allowable value or less by detecting a delay time difference between respective component signals constituting a video signal and controlling the delay time of each programmable delay line in accordance with the detecting level.

CONSTITUTION: Each of synchronizing signal extracting circuits 2a to 2c extracts a synchronizing signal from a video signal constituted of three component signals, e.g. a luminance signal and two color difference signals, each of delay time difference detecting circuits 3a, 3b detects a delay time difference between respective signals from the extracted synchronizing signals and each of delay time difference detecting level coding circuits 4a, 4b codes each detected output level into a code of n bits. The delay values of respective programmable delay lines 5a to 5c for setting up the delay values of respective component signals are set up by the codes. Consequently, the delay time difference between respective signals can be automatically set up to an allowable value or less.


Inventors:
TANJI AKITO
Application Number:
JP15021689A
Publication Date:
January 23, 1991
Filing Date:
June 13, 1989
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04N5/14; (IPC1-7): H04N5/14
Attorney, Agent or Firm:
Mamoru Takada (1 person outside)



 
Next Patent: JPH0314368