Title:
VIDEO SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP3667784
Kind Code:
B2
Abstract:
PURPOSE: To prevent a noise from being mixed in the video term of a video signal.
CONSTITUTION: A video signal Y2(τ) is converted into video data YD1 by an A/D conversion circuit 12 and stored in a line memory 13. The video data YD1 read from the line memory 13 are inputted to a clamp circuit 15 and inputted to an encoder circuit 18 after prescribed processing is conducted at a chrominance signal processing circuit 16 and a luminance signal processing circuit 17. Video data YD2 outputted from the encoder circuit 18 are converted into a video signal Y3(τ) by a D/A conversion circuit 19 and outputted. The timing of reading of video data YD1 in the line memory 13 is set while being delayed from the timing of write for a short period just for a delayed component generated by signal processing from the clamp circuit 15 to the encoder circuit 18 rather than a horizontal scanning period.
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Inventors:
Kazuo Ishimoto
Toru Watanabe
Toru Watanabe
Application Number:
JP3977394A
Publication Date:
July 06, 2005
Filing Date:
March 10, 1994
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H04N5/213; (IPC1-7): H04N5/213
Domestic Patent References:
| JP42285A |
Attorney, Agent or Firm:
Masamasa Shibano
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