Title:
VIDEO SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JPS6394786
Kind Code:
A
Abstract:
PURPOSE:To simply execute memory control without the need for a delay circuit and a changeover means by providing a serial input/serial output multi-port memory and a memory control circuit to allow the memory to execute input/ output operation. CONSTITUTION:An input data register 3a of the serial input/serial output multi- port memory 3 and an output data register 3c transfer a digital signal for one line of the memory cell array 3b with the memory cell array 3b altogether, and the memory control circuit 6 outputs a memory control signal to transfer the content of the input data register 3a storing a signal for one line of the memory cell array 3b by an input request signal to the memory cell array 3b or to transfer the signal for one line of the memory cell array 3b by an output request signal to the output data register 3c and outputs a clock or the like for input/output to the multi-port memory 3. Thus, no delay circuit nor changeover means is required.
Inventors:
WATABE KAZUYOSHI
Application Number:
JP24106786A
Publication Date:
April 25, 1988
Filing Date:
October 08, 1986
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04N5/262; G09G1/02; G09G5/00; G11C11/401; H04N5/907; H04N5/91; (IPC1-7): G09G1/02; H04N5/262; H04N5/907; H04N5/91
Attorney, Agent or Firm:
Kenichi Hayase