PURPOSE: To produce the 2nd video signal different from the input signal, by storing the supplied 1st video signal with every frame and successively and then reading the signal from the end of the even and odd fields each during the reading of the odd and even fields respectively.

CONSTITUTION: The 1st NTSC signal VBS1 is supplied to the A/D converting part 11 and the timing generating part 13, and the A/D-converted digital signal is stored in the memory part 12 under the control of the address setting part 14. The timing signal generated at the 2nd timing generating part 15 is supplied to the address setting part 16, the phase converting part 17 and the D/A converting part 18 each. Then the stored signal is read out of the part 12 under the control of the part 16 and then supplied to the part 17. At the part 17 a phase compensation is given to the color subcarrier between frames, and the reading is carried out form the end of the even and odd fields when reading the odd and even fields respectively. And then the D/A conversion 18 is carried out to deliver the 2nd video signal VBS2 which is reversed up and down to the signal VBS1.