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Title:
VIRTUAL MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH0561719
Kind Code:
A
Abstract:

PURPOSE: To facilitate the check of trace and to prevent the throughput of a computer from being lowered by the trace by reading an instruction after the virtual address of the instruction to be executed is stored in a trace memory.

CONSTITUTION: A virtual memory control mechanism 80 reads the virtual address of the instruction to be executed from a program 20 and reads the instruction at the virtual address after the address is stored in an instruction execution address tracer 60. A memory 30 is equipped with blocks 31-33 storing the process part of the program 20, and the virtual addresses of the memory blocks 31-33 or the virtual address of a data part 24 is stored in blocks 21-24 of the program 20. When executing the instruction, the virtual memory control mechanism 80 checks a control table 40 corresponding to the virtual addresses 21-23 of the process part containing the instruction, generates interruption when no operation is executed, reads the virtual addresses 21-23 or the like of the process part and sets them to a fault ID 50.


Inventors:
NAKADA NORIHEI
Application Number:
JP22048591A
Publication Date:
March 12, 1993
Filing Date:
August 30, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/28; G06F12/08; (IPC1-7): G06F11/28; G06F12/08
Domestic Patent References:
JPS60146341A1985-08-02
Attorney, Agent or Firm:
Umeo Yamauchi



 
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