To realize a viterbi decoder having improved characteristics/ performance due to high integration and small power consumption while having a normalized circuit capable of preventing generation of an overflow problem due to the accumulation of path metrics in an ACS arithmetic unit having parallel constitution capable of executing high-speed ACS operation even when restriction length is increased or the number of decoding bits is increased.

The viterbi decoder is provided with a maximum likelihood path metric detector 50 for detecting a maximum likelihood path metric from a pass-metric storage device in a process for executing ACS operation by the parallel ACS arithmetic unit and a maximum likelihood pass-metric storage device 60 for storing and resetting the maximum likelihood path metric in accordance with control. A branch-metric arithmetic unit 10, the storage device 60 and a subtractor 70 are arranged at the outside of the parallel ACS arithmetic unit.