Title:
VITERBI DECODER
Document Type and Number:
Japanese Patent JP3266182
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the throughput by using a means which executes the read, subtraction, addition and comparison/selection processings of the path metric value of an ACS circuit, a storage processing of the updated path metric value and also an updating processing of the minimum path metric value in a pipeline form and in parallel to each other.
SOLUTION: A path metric arithmetic part 2, i.e., a so-called ACS circuit, consists of an FF 28e and 28f which hold the outputs of adders 24 and 25 at the fall of a clock signal CLK, a comparator 26 which compares the output of the FF 28e with that of the FF 28f, a selector 27 which selects the smaller output, from the outputs of FF 28e and 28f, and an FF 28g which holds the output of the selector 27 at the rise of the signal CLK. In such a constitution, the FF 28a to 28g are inserted among the computing elements and the fall and rise of the signal CLK are alternately used. Thus, the operations are processed in a pipeline form and in parallel to each other. As a result, the single clock width can be reduced and the throughput is improved.
Inventors:
Yasuhiro Saegusa
Application Number:
JP15246197A
Publication Date:
March 18, 2002
Filing Date:
June 10, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06F11/10; H03M13/23; H03M13/41; (IPC1-7): H03M13/41; G06F11/10
Domestic Patent References:
| JP88402A | ||||
| JP936754A | ||||
| JP722969A | ||||
| JP746145A | ||||
| JP144056B2 |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)