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Patent Searching and Data


Title:
VOLTAGE CONTROLLED AMPLIFIER OUTPUT CLAMPING CIRCUIT OF DC-DC CONVERTER
Document Type and Number:
Japanese Patent JPH07227082
Kind Code:
A
Abstract:

PURPOSE: To reduce power supply output rising time by suppressing the change on activation of power supply of a feedback terminal voltage for determining the duty cycle of a switching element.

CONSTITUTION: When a power supply input V1 is effected, an output capacitor 12 is charged by the power supply input V1, a power supply output V0 gradually increases and hence the voltage of a feedback terminal 2 tends to increase via a phase compensation capacitor 11. At this time, even if an OP amplifier 8 tends to lower the output 17, the output 17 increases since it is pulled by the voltage increase of a feedback terminal 2. However, when the voltage of the feedback terminal 2 increases to some extent as compared with the voltage of the OP amplifier output 17 halfway during increase, a PNP transistor 18 continues, thus suppressing the voltage increase. The voltage of the terminal 2 reaches a value between the upper and lower limits of the voltage of a triangular waveform 7 and a comparator 9 outputs a rectangular waveform, thus switching a MOSFET 15 and immediately causing the power supply output V0 to rise.


Inventors:
Nomura, Ichiro
Application Number:
JP1994000013903
Publication Date:
August 22, 1995
Filing Date:
February 08, 1994
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
G05F1/56; H02M3/155; (IPC1-7): H02M3/155; G05F1/56
Attorney, Agent or Firm:
山口 巖