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Title:
VOLTAGE CONTROLLED OSCILLATION CIRCUIT
Document Type and Number:
Japanese Patent JPH0376310
Kind Code:
A
Abstract:

PURPOSE: To obtain a voltage controlled oscillating circuit whose operation is attained even at a low voltage region without using a differential comparator by supplying an input to a series connection circuit comprising enhancement P and N-channel FET pairs with a prescribed voltage range.

CONSTITUTION: The circuit consists of P-channel FETs Q1, Q3, Q5, N-channel FETs Q2, Q4, Q6 whose relevant gate and drain are connected directly, a resistive element R1 whose one terminal connects to the output 4 of a buffer amplifier 1 and whose other terminal connects to a gate connection point, and a capacitive element C1 whose one terminal is connected to each gate connecting point and whose other terminal is connected to ground. Through the constitution above, an input voltage (control voltage) VC is supplied between sources of FET Q1, Q2 and the voltage is selected to be lower than VTP+VTN (VTP is a threshold level of the FETs Q1, Q3 Q5 and VTN is a threshold level of the FETs Q2, Q4, Q6) and to be higher than the threshold level which is higher. Thus, a pulse train having a frequency corresponding to the input voltage is obtained from the output of the amplifier 1. That is, the circuit is operated even at a low voltage region lower than the sum of the threshold levels of the P and N-channel FETs.


Inventors:
KOIKE YUKIO
Application Number:
JP21228089A
Publication Date:
April 02, 1991
Filing Date:
August 18, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K3/354; (IPC1-7): H03K3/354
Attorney, Agent or Firm:
Uchihara Shin



 
Next Patent: JPH0376311