PURPOSE: To eliminate the risk of a latch-up state by charging two capacitors through FETs by a current source.

CONSTITUTION: When the output of an NOR gate 41 is at a logical level "1" and the output of an NOR gate 42 at a logical level "0", FETs 21 and 32 turn on and FETs 22 and 31 turn off; and a capacitor C52 contains no charge and a C51 is charged by the current source 11 through the FET21. Then once the capacitor is charged until the drain voltage of the FET31 exceeds the threshold voltage level of the NOR gate 41, the output of the NOR gate 41 is "0" and the output of the gate 42 is "1". Then, the FETs 22 and 32 turn off and the FETs 21 and 32 turn off. At this time, the C51 is discharged through the FET31 and the C52 is charged by the current source 11 through the FET22. Once the drain of the FET32 exceeds the threshold voltage V of the gate 42, the output of the gate 42 is "0" and the output of the gate 41 is "1", which is the last state. The C51 and C52 are charged and discharged repeatedly, but a potential lower than the ground level is not generated in the circuit, and there is no risk of the latch-up state.