Title:
VOLTAGE GENERATING CIRCUIT, DISPLAY DEVICE AND ELECTRONIC EQUIPMENT
Document Type and Number:
Japanese Patent JP3820944
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the area of a circuit which generates voltages for signal electrodes and to suppress voltage fluctuation.
SOLUTION: The voltage generating circuit is provided with a capacitor 4554 which holds the interline voltage of power feeding lines 4505 and 4506 when switches 4564 and 4568 are each closed between terminals a and c, a capacitor 4574 which back ups the holding voltage by the capacitor 4554 when the switches 4564 and 4568 are each closed between terminals b and c and an operational amplifier 4544 which conducts buffering for the intermediate voltage of power a feeding line 4504 and the power feeding line 4506. The back up voltage by the capacitor 4574 and the buffering voltage by the amplifier 4544 are made into parallel and outputted as (+Vx1) which is one of five voltages to be applied to the signal electrodes.
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Inventors:
Takashi Komozawa
Application Number:
JP2001275631A
Publication Date:
September 13, 2006
Filing Date:
September 11, 2001
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G02F1/133; G09G3/36; G09G3/20; (IPC1-7): G09G3/36; G02F1/133; G09G3/20
Domestic Patent References:
JP10161613A | ||||
JP9197366A | ||||
JP2150819A | ||||
JP2002318565A | ||||
JP2001343945A | ||||
JP11231279A | ||||
JP5198165A | ||||
JP5244767A |
Attorney, Agent or Firm:
川▲崎▼ 研二
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