Title:
電圧ランプ信号発生回路
Document Type and Number:
Japanese Patent JP4139447
Kind Code:
B2
Abstract:
A circuit (10) for generating a voltage ramp signal (VRAMP) having minimum amplitude variation over a large frequency range has been provided. The circuit includes a comparator (40) for comparing a voltage across a ramp capacitor (32) with a reference voltage. From the result of this comparison, a sampling capacitor (16) is discharged during the time that the voltage ramp signal is less than the reference voltage and charged during the time that the voltage ramp signal is greater than the reference voltage. The resulting voltage across the sampling capacitor is held and fed back to a transconductance amplifier (20) which adjusts the current that charges the ramp capacitor thereby adjusting the peak amplitude of the voltage ramp signal.
Inventors:
Park Con Dan
Wok van nip
Chi Man Lin
Wok van nip
Chi Man Lin
Application Number:
JP7836995A
Publication Date:
August 27, 2008
Filing Date:
March 10, 1995
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H03K4/501; H03K4/502
Domestic Patent References:
| JP6326565A | ||||
| JP5275985A |
Attorney, Agent or Firm:
Mamoru Kuwagaki