ボリュームデータ集合・レンダリング方法、ボリューム・グラフィックス・システム

Japanese Patent JP4158007

B2

Apparatus is provided to enable real-time volume rendering on a personal computer or a desktop computer in which a technique involving blocking of voxel data organizes the data so that all voxels within a block are stored at consecutive memory addresses within a single memory model, making possible fetching an entire block or data in a burst rather than one voxel at a time. This permits utilization of DRAM memory modules which provide high capacity and low cost with substantial space savings. Additional techniques including sectioning reduces the amount of intermediate storage in a processing pipeline to an acceptable level for semiconductor implementation. A multiplexing technique takes advantage of blocking to reduce the amount of data needed to be transmitted per block, thus reducing the number of pins and the rates at which data must be transmitted across the pins connecting adjacent processing modules with each other. A mini-blocking technique saves the time needed to process sections by avoiding reading entire blocks for voxels near the boundary between a section and previously processed sections.

Hugh See Lauer
Randy Bee Osborne
Hans Peter Pfister

JP2000207649A

October 01, 2008

July 10, 2000

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Terra Recon Incorporated

G06T1/20; G06T1/60; G06T15/00; G06T15/08; G06T15/40

JP9016805A
JP9512937A
JP4127284A
JP2284277A
JP63213091A

WO1996007989A1

金 喜都 外6名,“ピクセル並列処理によるボリューム・レンダリング向きの超高速専用計算機アーキテクチャ”,情報処理学会研究報告,日本,社団法人情報処理学会,第95巻,第80号,p.97-104

Michiharu Soga
Yutaka Ikeya
Hidetoshi Furukawa
Suzuki Kenchi
Keiro Mochizuki
Kajinami order
Taizo Shiraishi

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