Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
WAFER LEVEL CHIP-SIZE PACKAGE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2009059771
Kind Code:
A
Abstract:

To consolidate a process which requires a facility similar to the one used for the former process into a component in off-line.

By forming a plurality of LSI chips having an LSI region and a plurality of bonding pad regions on a semiconductor substrate on a wafer, an LSI wafer is completed. A plurality of post electrodes collectively connected to the plurality of bonding pad regions, interconnections respectively connected to the plurality of post electrodes, and a post electrode component with interconnections having a support for integrally supporting the plurality of post electrodes and the interconnections from a back side are formed. After collectively connecting the plurality of bonding pad regions and the plurality of post electrodes, resin sealing is performed. The interconnections are exposed by making a hole in the support, or peeling off from the support, external terminals connected to this exposed interconnection are formed. The plurality of interconnections is formed in the surface of the resin sealing portion.


Inventors:
Ishihara, Masamichi
Ueda, Hirotaka
Hashimoto, Kenji
Application Number:
JP2007000223876
Publication Date:
March 19, 2009
Filing Date:
August 30, 2007
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
KYUSHU INSTITUTE OF TECHNOLOGY
NAKAYA MICRODEVICES CORP
International Classes:
H01L23/12
Attorney, Agent or Firm:
大川 譲