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Title:
ウェハレベルパッケージ構造体およびセンサ装置
Document Type and Number:
Japanese Patent JP4867792
Kind Code:
B2
Abstract:

To provide a wafer-level package structure and sensor device that can attain a simplified manufacturing process as well as attaining a low process temperature, and attain an improved yield in a bonding process.

In a wafer-level package structure 100, metallic layers 18 and 28 for sealing a sensor wafer 10 and a primary package wafer 20 and electrical connection metallic layers 19 and 29 are mutually connected at normal temperature. Each of the sealing metallic layers 18 and 28 and each of the electrical connection metallic layers 19 and 29 are respectively made up, on insulating films 16 and 23, of a film laminated by a lower layer that is formed by a material selected from a group of Ti, Cr, Nb, Zr, TiN, and TaN, and an Au film as an upper layer formed such that its surface RMS roughness is 1.8 nm or less. The sensor device is formed by dividing the wafer-level package structure 100 into a prescribed desired size based on the size of a sensor substrate (sensor main body) 1 in the sensor wafer 10.

COPYRIGHT: (C)2009,JPO&INPIT


Inventors:
Takeshi Yoshi
Ryo Tomoda
Toru Baba
Takashi Okudo
Application Number:
JP2007138276A
Publication Date:
February 01, 2012
Filing Date:
May 24, 2007
Export Citation:
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Assignee:
Panasonic Electric Works Co., Ltd.
International Classes:
H01L23/02; B81B3/00; G01P15/08; G01P15/12; H01L29/84; H01L37/00
Domestic Patent References:
JP2006525133A
JP2006222436A
JP2005500172A
JP2001150398A
JP2001068616A
JP3938203B1
JP3938206B1
Other References:
Symposium on Microjoining and Assembly Technology in Electronics,Vol.4th,PAGE.163-166,1998
Attorney, Agent or Firm:
Keisei Nishikawa



 
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