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Title:
WAFER MAP AUTOMATIC DISCRIMINATION CONTROL METHOD, SEMICONDUCTOR INSPECTION APPARATUS, SEMICONDUCTOR MANUFACTURING APPARATUS, AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2004303987
Kind Code:
A
Abstract:

To provide a wafer map automatic discrimination control method and a semiconductor inspection apparatus for automatically and properly detecting the tendency of a wafer map, and to provide a semiconductor manufacturing apparatus and a semiconductor device.

A flowchart indicating the wafer map automatic discrimination control method includes a step S1 of acquiring positional information for discriminating a defective part of a semiconductor wafer in response to an inspection mode of a defect inspection apparatus or the like; a map processing step of dividing the surface of the semiconductor wafer into areas on information processing by a map processing process, and overlapping the result on the fault location information obtained by the defect inspection apparatus as shown in a step S2; an arithmetic processing step in a step 5 of discriminating whether or not the density or the number of defective parts exceeds a preset reference value on the basis of the positional information in the step S1 for each area in the step S2, and displaying the result in a way capable of identifying the inside of the reference value and the other parts; and a defective area information acquisition step in the step S5 of carrying out identification purpose display control for areas discriminated in excess of the reference value, and areas adjacent to the discriminated areas respectively as areas with defective tendency.


Inventors:
NAGATSUKA YOSHINORI
Application Number:
JP2003095962A
Publication Date:
October 28, 2004
Filing Date:
March 31, 2003
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
G01N21/956; H01L21/66; (IPC1-7): H01L21/66; G01N21/956
Attorney, Agent or Firm:
Masahiko Ueyanagi
Fujitsuna Hideyoshi
Osamu Suzawa