Title:
ウェーハの研磨方法及びシリコンウェーハ
Document Type and Number:
Japanese Patent JP7306234
Kind Code:
B2
Abstract:
Provided is a wafer polishing method capable of improving nanotopography characteristics within a site on the surface of a wafer having a 2 mm square area or a small area equivalent thereto and a silicon wafer polished by the wafer polishing method, and further provided is a method of chemical-mechanical polishing the surface of a wafer through a polishing step in two or more polishing steps with different polishing rates, in which the in-plane thickness variation (standard deviation) of a polishing pad 150 used in a polishing step with a machining allowance of 0.3 μm or more is 2.0 μm or less.
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Inventors:
Kazuaki Osasa
Katsuhisa Sugimori
Kazuki Nishioka
Takeshi Morita
Katsuhisa Sugimori
Kazuki Nishioka
Takeshi Morita
Application Number:
JP2019208657A
Publication Date:
July 11, 2023
Filing Date:
November 19, 2019
Export Citation:
Assignee:
Sumco inc.
International Classes:
H01L21/304; B24B37/10; B24B37/20
Domestic Patent References:
| JP2003257908A | ||||
| JP2006142474A | ||||
| JP2007266235A | ||||
| JP2017112302A | ||||
| JP2011155265A |
Foreign References:
| WO2016076404A1 |
Attorney, Agent or Firm:
Mitsuhiro Washito
Ogata Japanese
Ogata Japanese
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