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Patent Searching and Data


Title:
WAFER-SCALE INTEGRATED CIRCUIT DEVICE AND METHOD OF WIRING BETWEEN ELEMENT CHIPS
Document Type and Number:
Japanese Patent JPH0629390
Kind Code:
A
Abstract:

PURPOSE: To form a ring network, by providing a plurality of element chips on a semiconductor substrate, a going-out logic circuit and a coming-in logic circuit, an external control unit for controlling the element chips to form a chip row.

CONSTITUTION: Going-out logic circuits 31a to 37a and coming-in logic circuits 31b to 37b are amounted on element chips 210 to 216. While each element chip is put to a test, going-out logic circuits included in adjoining element chips are connected to each other, and coming-in logic circuits included in adjoining element chips are also connected to each other so that each one-dimensional chip row is formed. Moreover, in the last element chip the going-out logic circuit and the coming-in logic circuit are connected to form a ring network.


Inventors:
HIROSE YOSHIO
Application Number:
JP18504692A
Publication Date:
February 04, 1994
Filing Date:
July 13, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/82; H01L21/822; H01L27/04; (IPC1-7): H01L21/82; H01L27/04
Attorney, Agent or Firm:
Teiichi