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Title:
WAFER TRAY, WAFER BURN-IN UNIT, WAFER-LEVEL BURN-IN APPARATUS USING SAME UNIT, AND TEMPERATURE CONTROLLING METHOD OF SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JP2005347612
Kind Code:
A
Abstract:

To subject a plurality of semiconductor devices formed on a wafer to a burn-in test under a uniform-temperature condition and in a lump as the wafer, while suppressing the variations of the self-heat-generation distribution of the wafer which are caused by faulty chips.

A wafer tray 4 comprises a wafer chuck 1 and a uniformly heating wafer 2. When performing a burn-in test, a semiconductor wafer 3 is so held that the rear surface of the semiconductor wafer 3 is contacted oppositely with the rear surface of the uniformly heating wafer 2. On the principal surface of the uniformly heating wafer 2, a plurality of uniformly heating devices 5 each of which comprises a temperature sensor and a heat generating body are formed in the form of a grid, and the temperature distribution generated in the surface of the held semiconductor wafer 3 can be measured particularly. Further, the semiconductor wafer 3 can be heated locally. Consequently, since the temperature generated in the surface of the semiconductor wafer 3 can be made uniform, a wafer-level burn-in test can be performed under a uniform temperature condition.


Inventors:
SANADA MINORU
SEGAWA AKITSUGU
Application Number:
JP2004167001A
Publication Date:
December 15, 2005
Filing Date:
June 04, 2004
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/66; H01L21/68; H01L21/683; (IPC1-7): H01L21/66; H01L21/68
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori