Title:
WAFER TREATMENT MODULE AND WAFER TREATMENT METHOD
Document Type and Number:
Japanese Patent JPH04226049
Kind Code:
A
Abstract:
PURPOSE: To provide a means, wherein a chance of fine dust, caused accompanying a handling work or being in an atmosphere, to stick on the surface of a wafer is reduced as much as possible by processing a wafer in a high vacuum environment. CONSTITUTION: This wafer processing module comprises a vacuum-tight module chamber 102, at least one processing station 104, at least one load lock 12 holding a wafer, and a transfer means 28 which transfers the wafer faced down between the processing station 104 and the load lock 12. The module processes under, high vacuum from loading until unloading, while the effect of particles generated during handling work is reduced.
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Inventors:
SESHIRU JIEI DEEBISU
TEIMOSHII EI UURUDORITSUJI
DOYUAN II KAATAA
JIYON II SUPENSAA
ROBAATO MACHIYUUZU
RANDOORU SHII HIRUDENBURANDO
TEIMOSHII EI UURUDORITSUJI
DOYUAN II KAATAA
JIYON II SUPENSAA
ROBAATO MACHIYUUZU
RANDOORU SHII HIRUDENBURANDO
Application Number:
JP10134791A
Publication Date:
August 14, 1992
Filing Date:
May 07, 1991
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L21/677; B25J15/08; B65G1/00; B65G1/02; B65G1/04; B65G1/07; B65G49/00; B65G49/07; C23C14/56; C23C16/44; C23F4/00; H01L21/00; H01L21/67; H01L21/68; H01L21/687; (IPC1-7): B65G1/02; B65G1/04; C23C14/56; C23F4/00; H01L21/68
Domestic Patent References:
| JPS60175411A | 1985-09-09 | |||
| JPS57149748A | 1982-09-16 | |||
| JPS59208837A | 1984-11-27 | |||
| JPS5994435A | 1984-05-31 | |||
| JPS57145321A | 1982-09-08 |
Attorney, Agent or Firm:
Akira Asamura (2 outside)