Title:
WAFER AND WAFER MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2023030360
Kind Code:
A
Abstract:
To provide a wafer and a wafer manufacturing method capable of suppressing the remaining of a resist layer used for forming a conductive bump.SOLUTION: A wafer includes a substrate having a first surface provided with a first region in which a plurality of effective chip regions are arranged and a second region provided around the first region, a plurality of first conductive bumps provided on the first surface of the substrate within the first region, and a plurality of second conductive bumps provided on the first surface of the substrate within the second region, and in plan view from a direction perpendicular to the first surface, the areal density of the second conductive bumps in the second region is lower than the areal density of the first conductive bumps in the first region.SELECTED DRAWING: Figure 11
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Inventors:
YAMAMOTO KENGO
Application Number:
JP2021135446A
Publication Date:
March 08, 2023
Filing Date:
August 23, 2021
Export Citation:
Assignee:
SHINKO ELECTRIC IND CO
International Classes:
H01L21/60
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Tadahiko Ito
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