Title:
【発明の名称】論理合成支援方法およびシステム
Document Type and Number:
Japanese Patent JP3101872
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To correct/synthesize function description files described through the use of a function description language, to improve work efficiency for operating a logic synthesis processing and to reduce the number of processes in circuit design. SOLUTION: A logic synthesis part 2 logically synthesizes the HDL(hardware description language) files BF, SF1 and SF2 different in description systems. The HDL files BF, SF1 and SF2 are divided for respective function units and are described. Logic synthesis is executed by dividing it for the respective function units. An area check part 3 and a delay check part 4 calculate areas and delay time from the synthesis result of the logic synthesis part 2. A check result comparison part 5 and an HDL judgment part 6 compare the obtained area and delay time with the desire of a designer, and discriminate those fitted to the desired element characteristic of the designer for the respective function units. An HDL selection part 7 selectively extracts and connects pertinent function unit parts from respective HDL files BF, SF1 and SF2 and generates new HDL description.
Inventors:
Hisashi Maeda
Application Number:
JP19250597A
Publication Date:
October 23, 2000
Filing Date:
July 17, 1997
Export Citation:
Assignee:
NEC Engineering Co., Ltd.
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP822483A | ||||
| JP520379A | ||||
| JP10177588A |
Other References:
野地保、外３名，”機能設計を対象とする合成予測の実現”，電子情報通信学会論文誌Ｄ−▲Ｉ▼，平成７年７月，第Ｊ７８−Ｄ−▲Ｉ▼巻，第７号，ｐ．５８８−５９６
Attorney, Agent or Firm:
Seigo Suzuki