PURPOSE: To suppress the increase of the hardware quantity by monitoring plural information processors by a watch dog timer for holding a first state in response to a synchronizing signal, and holding a second state in response to a reset signal.

CONSTITUTION: As for synchronizing signals 31, 32 generated from information processors 1, 2, its synchronizing state is deteriorated, when a fault is generated, and a watch dog timer 3 detects a faulty state thereby. FFs 301, 302 are set, when the signals 31, 32 are inputted to terminals S, and an output is held in H. When a reset signal 33 is inputted to terminals R, the FFs are reset, and the output is held in L. A counter 306 is initialized in response to an input of the signal 33 and starts time counting, and when the time counting value becomes higher than a prescribed value, an overflow signal 34 is sent out. When the signal 34 is inputted, and an output of a counter control circuit 303 is L, an AND circuit 307 sends out an abnormal signal 37, and when the signal 34 is inputted, and an output of a counter control circuit 304 is L, an AND circuit 308 sends out an abnormal signal 38.