Title:
STATIC RANDOM ACCESS MEMORY
Document Type and Number:
Japanese Patent JP3230848
Kind Code:
B2
Abstract:
PURPOSE: To improve the degree of integration with a low power consumption by providing a data storage means which is connected to one bit line through a single input/output node and a single switching means in a memory cell.
CONSTITUTION: A data storage circuit consists of two cross coupled inverters made up with transistors Q1 and Q2 and resistances R1 and R2. A common connection node N1 of the transistor Q2 and the resistance R2 are configured with a single input/output node of the data storage circuit. A transistor Q3 is connected between the node N1 and a single bit line BL and operates in accordance with the signals on word lines WLi. A transistor Q7 operates in accordance with output column selection signals Yi of a column recorder 6. In accordance with column address signals CAO to CAn, a source line potential controlling circuit 8 gives a prescribed intermediate potential or a ground potential to the source of the transistors Q1 and Q2. Having this constitution, the degree of integration in a static random memory is improved.
Inventors:
Kenji Anami
Application Number:
JP23854792A
Publication Date:
November 19, 2001
Filing Date:
September 07, 1992
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G11C11/413; G11C11/412; G11C11/418; G11C11/419; (IPC1-7): G11C11/413
Domestic Patent References:
| JP6383992A | ||||
| JP56143587A | ||||
| JP5661088A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)