PURPOSE: To decrease the capacity of a required storage element, to simplify the circuit and to reduce the cost of the circuit by selecting only the signal corresponding to the input data of certain series in one or plural shift registers and parallel outputs therefrom outputting the selected signal as an address signal of the storage element.

CONSTITUTION: A π/4 phase shift signal is formed by repeating a phase shift between an optional point among four points marked in a black dot and an optional point among four points marked in a white round alternately. Thus, input signals of a waveform shaping circuit are binary values of ±1/20.5 and three values of 0 and ±1 repeated alternately, and the cases are classified into the case of tri-state values for an even number stage and binary values for an odd number stage and case of binary values for an even number stage and tri-state values for an odd number stage. Then a selector 11 selects an output 6b of an even number stage of shift register 1b when the tri-state values are obtained from an even number stage of the register and an output 6c of an odd number stage of shift register 1b when the tri-state values are obtained from an odd number stage of the register, the resulting signal is obtained as a signal 17, which is inputted to a ROM 3. When the outputs are classified into two ways, a clock signal 18 having a half of the data rate of the input signals 5a, 5b is inputted to the selector 11 and the ROM 3.