To provide a circuit which can avoid a problem such as disappearance of pulses of an output signal of a duty control buffer.

The circuit includes a duty control buffer 10 which receives input signals IN1, INB1, and a duty control voltage generating section 20 which receives outputs OUT1, OUTB1 of the duty control buffer, detects a duty error and generates control signals VCNT1, VCNTB1. The duty control buffer 10 includes: a differential stage having a first differential pair and a second differential pair for receiving the input signals by differentiation; a load element pair to which an output pair of the first differential pair and an output pair of the second differential pair are connected and which is connected between the output pairs of the first and second differential pairs and the power supply; and a current source stage which supplies drive current to the first and second differential pairs. An imbalanced differential pair is configured by a pair of transistors of the first differential pair having different current drive capabilities and a pair of transistors of the second differential pair having different current drive capabilities.

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