PURPOSE: To perform proper re-timing with less deterioration of waveform by providing an intermediate re-timing circuit in the middle of multiple cascade- connected circuits and supplying the output clock of the frequency dividing circuit of the corresponding stage to the intermediate re-timing circuit as a re-timing clock with no substantial delay.

CONSTITUTION: Since re-timing is performed by means of an intermediate re- timing circuit 27 by means of the Q-output of a frequency dividing circuit 12n-m irrespective of the transfer of the input pattern of the circuit 27, each delay time after a multiplex circuit 14m+1 can be used as delay time for obtaining multiplex controlling clocks to multiplex circuits succeeding the circuit 27. Therefore, the delay time of a delay circuit 15n for obtaining the multiplex controlling clock to the multiplex circuit 14n in the final stage becomes τn+τn-1+...+τn-1 having no relation with the delay time of the pattern of each section on the preceding side of the circuit 14n and, as a result, the delay time of a delay circuit 15n for obtaining the re-timing clock to a retiming circuit 16 becomes τm+...+τn+T0 which is remarkably smaller than the conventional delay time.