Title:
WIRING BOARD
Document Type and Number:
Japanese Patent JP3163707
Kind Code:
B2
Abstract:
PURPOSE: To make the smoothing process unnecessary for the remaining uneven solder on the bonding pad when the IC chip rejected as a defective is replaced with another IC chip.
CONSTITUTION: A wiring board 11 is of such a structure that two sets of bonding pads in total, a pair of the main bonding pads 14a and 14b and a pair of the sub-bonding pads 15a and 15b, are arranged in parallel on a board 12 with respect to a pair of electrodes of one IC chip to be mounted on it. Therefore, when one IC chip should be replaced with another chip and removed from the board 11 after the electrodes of this IC chip are fixed to the main bonding pads 14a and 14b through solder bumps, it is possible to fix the electrodes of another IC chip to the sub-bonding pads 15a and 15b through solder bumps even if the solder remains unevenly on the main bonding pads 14a and 14b.
Inventors:
Koichi Saito
Application Number:
JP36053591A
Publication Date:
May 08, 2001
Filing Date:
December 30, 1991
Export Citation:
Assignee:
CASIO COMPUTER CO.,LTD.
International Classes:
H01L21/60; H05K3/34; H05K1/00; H05K1/11; (IPC1-7): H01L21/60
Domestic Patent References:
| JP6265835U |
Attorney, Agent or Firm:
Hanawa Yoshio