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Patent Searching and Data


Title:
WIRE-BONDING METHOD IN SEMICONDUCTOR INTEGRATED CIRCUIT ASSEMBLY AND WIRE-BONDING DEVICE USED THEREFOR
Document Type and Number:
Japanese Patent JPS6218048
Kind Code:
A
Abstract:

PURPOSE: To improve efficiency in wire-bonding work and precision of coupling positions, by bonding the tip-end parts of wires with chip-side electrode pads, bonding the extending parts of wires with base-side electrode pads, and then cutting extra-extended parts of the wires.

CONSTITUTION: A pair of rails 1-1 are installed extending through a wire- bonding work station S on a bed B. And freely-movable supporting boards 2, on which a chip-mounting base P is mounted with a semiconductor chip 3 jointed on a package base 4, are set on the rails 1-1. And these supporting boards 2 are moved intermittently in turn so that a chip-mounting base p can be intermittently carried to the wire-bonding work station S, and a wire compression bonder A is arranged on the upper side of the station S. On the central part of a package base 4 in a rectangular-plate shape, the semiconductor chip 3 is connected in smaller rectangular-plate shape, to form the chip-mounting base P.


Inventors:
USAMI TAMOTSU
Application Number:
JP15598885A
Publication Date:
January 27, 1987
Filing Date:
July 17, 1985
Export Citation:
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Assignee:
FUJI KEIEI SYST KK
International Classes:
H01L21/603; H01L21/60; (IPC1-7): H01L21/60
Domestic Patent References:
JPS5141959A1976-04-08
JPS4727471A
Attorney, Agent or Firm:
Takefumi Tanaka