Title:
RECEPTION AGC CIRCUIT
Document Type and Number:
Japanese Patent JP3218474
Kind Code:
B2
Abstract:
PURPOSE: To obtain the AGC circuit minimizing a BER (decoding bit error rate) after error correction in a synchronization detection PSK demodulation receiver.
CONSTITUTION: This circuit is provided with synchronization detection PSK demodulators 1-4 implementing soft discrimination demodulation, coding rate variable error correction circuits 7, 8 decoding demodulated soft discrimination data to correct an error of reception data, and an AGC circuit 10 provided with a reference level selected depending on each coding rate and comparing a reference level selected by a coding rate selection signal with the soft discrimination data to control a variable attenuator 2, and the circuit absorbs level fluctuation in a reception signal and optimizes the soft discrimination data to make the BER best.
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Inventors:
Akihiro Higashiyama
Application Number:
JP31377991A
Publication Date:
October 15, 2001
Filing Date:
October 31, 1991
Export Citation:
Assignee:
NEC Engineering Co., Ltd.
International Classes:
H03G3/30; H03G3/20; (IPC1-7): H03G3/20
Domestic Patent References:
| JP6079813A | ||||
| JP3162115A | ||||
| JP4196929A |
Attorney, Agent or Firm:
Suzuki Akio