To reduce labor and cost for mounting resistors and to reduce the area of a substrate in a wiring substrate capable of selectively mounting switching elements of different sorts.
In the wiring board 80, lands 25, 27, 29, 31, 33, 35 and lands 26, 28, 30, 32, 34, 36 are respectively arranged on a first straight line L1 and a second straight line L2 which are respectively extended in the back-and-forth direction successively from the front to the rear. The lands 25 to 36 are arranged so that a third straight line L3 connecting the land 25 to the land 26, a fourth straight line L4 connecting the land 27 to the land 28, a fifth straight line L5 connecting the land 29 to the land 30, a sixth straight line L6 connecting the land 31 to the land 32, a seventh straight line L7 connecting the land 33 to the land 34, and an eighth straight line L8 connecting the land 35 to the land 36 are parallel with each other. A multiple-chip resistor is mounted on the lands 25 to 32 in the case of mounting a transistor, and a multiple-chip resistor is mounted on the lands 29 to 36 in the case of mounting an FET.
HASEGAWA TAKAHIKO
JP2005101082A | 2005-04-14 | |||
JPH09199301A | 1997-07-31 | |||
JP2004200205A | 2004-07-15 | |||
JP2003273480A | 2003-09-26 | |||
JP2007528817A | 2007-10-18 | |||
JP2003158350A | 2003-05-30 | |||
JP2005057011A | 2005-03-03 |
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