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Patent Searching and Data


Title:
WIRING CHECKER
Document Type and Number:
Japanese Patent JPS5616877
Kind Code:
A
Abstract:

PURPOSE: To make it possible to make a unit small-size and check wiring rapidly and surely, by not using a relay and a magnetic tape but using an electronic circuit and a microcomputer.

CONSTITUTION: Data of wiring contents of tested unit UNT stored in memory MEM is output to the data bus successively for every address by the operation of the CPU. The first address information is latched in latch circuit LAT for a prescribed time. The output corresponding to this address information is selected by decoder DEC1, and FF1 outputs "1". Bus driver unit BDU is selected through OR gate ORG1, and the "1" level output of FF1 is applied to BDU1, and data from the data bus which is latched in data latch circuit DLT1 is applied to the pertinent terminal of unit UNT. Next, a bus driver unit other than unit BDU1 is selected by decoder DEC2, and data at the pertinent terminal of unit UNT is taken out and is compared with corresponding data of memory MEM, and the comparison result is displayed on display unit DSP. After that, the similar operation is performed while switching selection of DEC1.


Inventors:
NARITA FUKUO
Application Number:
JP9257579A
Publication Date:
February 18, 1981
Filing Date:
July 23, 1979
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G01R31/02; G06F11/22; (IPC1-7): G01R31/02; G06F11/22